Isolation techniques for reducing dark current in CMOS image sensors

ABSTRACT

Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

FIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductor devices,and more particularly, to trench isolation technology for use insemiconductor devices, including CMOS image sensors.

BACKGROUND OF THE INVENTION

[0002] In silicon integrated circuit (IC) fabrication, it is oftennecessary to isolate semiconductor devices fromed in the substrate. Thisis true for many semiconductor memory devices, for example, DRAM, flashmemory, SRAM, microprocessors, DSP and ASIC. The individual pixels of aCMOS image sensor also need to be isolated from each other.

[0003] A CMOS image sensor circuit includes a focal plane array of pixelcells, each one of the cells including a photogate, photoconductor, orphotodiode overlying a charge accumulation region within a substrate foraccumulating photo-generated charge. Each pixel cell may include atransistor for transferring charge from the charge accumulation regionto a floating diffusion node and a transistor, for resetting thediffusion node to a predetermined charge level prior to chargetransference. The pixel cell may also include a source followertransistor for receiving and amplifying charge from the diffusion nodeand an access transistor for controlling the readout of the cellcontents from the source follower transistor.

[0004] In a CMOS image sensor, the active elements of a pixel cellperform the necessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge from the floatingdiffusion node. Photo charge may be amplified when it moves from theinitial charge accumulation region to the floating diffusion node. Thecharge at the floating diffusion node is typically converted to a pixeloutput voltage by a source follower output transistor. Thephotosensitive element of a CMOS image sensor pixel is typically eithera depleted p-n junction photodiode or a field induced depletion regionbeneath a photogate. A photon impinging on a particular pixel of aphotosensitive device may diffuse to an adjacent pixel, resulting indetection of the photon by the wrong pixel, i.e. cross-talk. Therefore,CMOS image sensor pixels must be isolated from one another to avoidpixel cross talk. In the case of CMOS image sensors, which areintentionally fabricated to be sensitive to light, it is advantageous toprovide both electrical and optical isolation between pixels.

[0005] CMOS image sensors of the type discussed above are generallyknown as discussed, for example, in Nixon et al., “256.times.256 CMOSActive Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-StateCircuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOSActive Pixel Image Sensors,” IEEE Transactions on Electron Devices,Vol.41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and6,204,524, which describe operation of conventional CMOS image sensors,the contents of which are incorporated herein by reference.

[0006] Shallow trench isolation (STI) is one technique, which can beused to isolate pixels, devices or circuitry from one another. Ingeneral, a trench is etched into the substrate and filled with adielectric to provide a physical and electrical barrier between adjacentpixels, devices, or circuitry. Refilled trench structures, for example,are formed by etching a trench by a dry anisotropic or other etchingprocess and then filling it with a dielectric such as a chemical vapordeposited (CVD) silicon dioxide (SiO₂). The filled trench is thenplanarized by an etch-back process so that the dielectric remains onlyin the trench and its top surface remains level with that of the siliconsubstrate. The depth of a shallow trench is generally from about 2000 toabout 2500 Angstroms.

[0007] One drawback associated with shallow trench isolation in the caseof CMOS image sensors is cross-talk from a photon impinging on aparticular pixel of a photosensitive device causing changes that maydiffuse under the shallow trench isolation structure to an adjacentpixel. Another drawback is that a hole accumulation layer along thesidewall of the trench is relatively small since it is limited by thedepth of the shallow trenches.

[0008] One technique which may be used to improve pixel isolation inCMOS image sensors is to implant dopants beneath the isolation region;however, it has been found that this may contribute undesirably to pixeldark current. Minimizing dark current in the photodiode is a key deviceoptimization step in CMOS image sensor fabrication.

[0009] It is desirable to provide an isolation technique that preventscross-talk between pixels while reducing dark current or current leakageas much as possible. It is also desirable to provide an isolationtechnique while increasing a hole accumulation region adjacent a pixelisolation region.

BRIEF SUMMARY OF THE INVENTION

[0010] In one aspect, the invention provides a structure for isolatingareas in a semiconductor device having a trench filled with a conductivematerial containing silicon formed in an active layer of a substrate toisolate adjacent regions. The conductive material containing silicon maybe doped with n-type or p-type dopants prior to or after deposition ofthe material. Preferred conductive materials containing silicon includepolysilicon and silicon-germanium. In another aspect, the inventionprovides forming a trench adjacent an active layer of a substrate,growing an epitaxial layer to partially fill the trench and depositingan insulating material over the epitaxial layer and within the trench tocompletely fill the trench.

[0011] These and other features and advantages of the invention will bemore apparent from the following detailed description that is providedin connection with the accompanying drawings and illustrate exemplaryembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1A is a top plan view of an exemplary CMOS image sensorfragment;

[0013]FIG. 1B is a diagrammatic side sectional view of the FIG. 1A imagesensor fragment taken along line 1B-1B;

[0014]FIG. 2 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench in process in accordance with a thirdembodiment of the present invention;

[0015]FIG. 3 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench at a processing step subsequent to thatshown in FIG. 2;

[0016]FIG. 4 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench at a processing step subsequent to thatshown in FIG. 3;

[0017]FIG. 5 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench at a processing step subsequent to thatshown in FIG. 3;

[0018]FIG. 6 is a diagrammatic side sectional view of a CMOS imagesensor fragment incorporating the trench of FIGS. 4 and 5;

[0019]FIG. 7 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench in process in accordance with a secondembodiment of the present invention;

[0020]FIG. 8 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench at a processing step subsequent to thatshown in FIG. 7;

[0021]FIG. 9 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench at a processing step subsequent to thatshown in FIG. 8;

[0022]FIG. 10 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench at a processing step subsequent to thatshown in FIG. 9;

[0023]FIG. 11 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench at a processing step subsequent to thatshown in FIG. 10;

[0024]FIG. 12 is a diagrammatic side sectional view of a CMOS imagesensor fragment showing a trench in process in accordance with a thirdembodiment of the present invention at a processing step subsequent tothat shown in FIG. 10;

[0025]FIG. 13 is a diagrammatic side sectional view of a CMOS imagesensor fragment incorporating the trench of FIG. 12;

[0026]FIG. 14 is a diagrammatic side sectional view of a CMOS imagesensor fragment incorporating the trench of FIG. 13; and

[0027]FIG. 15 is a schematic diagram of a processor system incorporatinga CMOS image sensor constructed in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028] In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way, of illustration of specific embodiments in which the inventionmay be practiced. These embodiments are described in sufficient detailto enable those skilled in the art to practice the invention, and it isto be understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0029] The terms “wafer” and “substrate” are to be understood asincluding silicon, silicon-on-insulator (SOI), or silicon-on-sapphire(SOS) technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium-arsenide.

[0030] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an image sensor will proceedsimultaneously in a similar fashion.

[0031] Applicants propose several trench isolation techniques to isolateareas of semiconductor devices and in an exemplary embodiment tominimize dark current and suppress leakage current in CMOS imagesensors, as described below with reference to FIGS. 2-15. To betterillustrate these techniques, a brief description of an exemplary CMOSimage sensor pixel is described first with reference to FIGS. 1A and 1Bhereinbelow. However, it should be noted that the invention is notlimited to CMOS image sensors and may be used in any suitable device,for example, a DRAM, flash memory, SRAM, microprocessor, DSP or ASIC.

[0032] Referring now to FIGS. 1A and 1B, a semiconductor wafer fragmentof an exemplary CMOS image sensor four-transistor (4T) pixel, generallydesignated by reference numeral 10, is shown. It should be noted thatwhile FIGS. 1A-1B show the use of a transfer gate 50 and associatedtransistor, the transfer gate 50 provides advantages, but is notrequired. Thus, the invention may be used in any CMOS imager including,for example, a three transistor (3T) environment where the transfer gateis omitted and an n-type charge collection region of a photodiode isconnected with an n-type diffusion region 21. The CMOS image sensor 10generally comprises a charge collection region 21 for collecting chargesgenerated by light incident on the pixel and transfer gate 50 fortransferring photoelectric charges from the collection region 21 to asensing node, typically a floating diffusion region 25. The floatingdiffusion region is electrically connected to the gate of an outputsource follower transistor. The pixel also includes a reset transistor40 for resetting the sensing node to a predetermined voltage beforesensing a signal, a source follower transistor 60 which receives at itsgate an electrical signal from the sensing node 25, and a row selecttransistor 80 for outputting a signal from the source followertransistor 60 to an output terminal in response to an address signal.

[0033] The exemplary CMOS image sensor uses a pinned photodiode as thecharge collection region 21. The pinned photodiode is termed such sincethe potential in the photodiode is pinned to a constant value when thephotodiode is fully depleted. The pinned photodiode has a photosensitiveor p-n-p junction region comprising a p-type surface layer 24 and ann-type photodiode region 26 within a p-type active layer 20. The pinnedphotodiode includes two p-type regions 20, 24 so that the n-typephotodiode region is fully depleted at a pinning voltage. Impurity dopedsource/drain regions 22, preferably having n-type conductivity, areprovided about the transistor gates 40, 60, 80. The floating diffusionregion 25 adjacent to transfer gate 50 is also preferable n-type.

[0034] In a typical CMOS image sensor, trench isolation regions 28formed in the active layer 20 are used to isolate the pixels. FIGS. 1Aand 1B illustrate typical STI isolation trenches 28. The trenchisolation regions 28 are formed using a typical STI process and aregenerally formed by etching a trench in the doped active layer orsubstrate 20 via a directional etching process, such as Reactive IonEtching (RIE), or etching with a preferential anisotropic etchant usedto etch into the doped active layer 20 to a sufficient depth, generallyabout 1000 to 3000 Angstroms.

[0035] The trenches are then filled with an insulating material, forexample, silicon dioxide, silicon nitride, ON (oxide-nitride), NO(nitride-oxide), or ONO (oxide-nitride-oxide).

[0036] The gate stacks for the pixel transistors are formed before orafter the trench is etched. The order of these preliminary process stepsmay be varied as is required or convenient for a particular processflow, for example, if a known photogate sensor (not shown) whichoverlaps the transfer gate is desired, the gate stacks must be formedbefore the photogate, but if a non-overlapping photogate is desired, thegate stacks may be formed after photogate formation.

[0037] A translucent or transparent insulating layer 30 is formed overthe CMOS image sensor. Conventional processing methods are then carriedout to form, for example, contacts 32 (shown in FIG. 1A) in theinsulating layer 30 to provide an electrical connection to thesource/drain regions 22, the floating diffusion region 25, and otherwiring to connect gate lines and other connections in the sensor 10. Forexample, the entire surface may then be covered with a passivation layerof e.g., silicon dioxide, BSG, PSG, or BPSG, which is planarized andetched to provide contact holes, which are then metallized to providecontacts to the photogate (if used), reset gate, and transfer gate.

[0038] In CMOS image sensors depicted in FIGS. 1A and 1B, electrons aregenerated by light incident externally and stored in the n-typephotodiode region 26. These charges are transferred to the diffusionnode 25 by the gate structure 50 of the transfer transistor. The sourcefollower transistor produces an output signal from the transferredcharges. A maximum output signal is proportional to the number ofelectrons extracted from the n-type photodiode region 26. The maximumoutput signal increases with increased electron capacitance oracceptability of the photodiode. The electron capacity of pinnedphotodiodes typically depends on doping levels and the dopants implantedto form regions 24, 26, 20.

[0039] A problem associated with the shallow trench isolation techniqueis photon diffusion under the shallow trench isolation structure fromone pixel to an adjacent pixel. Attempts have been made to enhanceisolation by implanting ions beneath the shallow trench isolationstructure. However, these implants result in high current leakage. Theinvention provides a novel technique for improved isolation betweenadjacent pixels that does not require additional implants beneath thetrench, thereby minimizing the generation of dark current in the CMOSimage sensor.

[0040] Another consideration in CMOS image sensor fabrication areisolation design rules are constructed to make sure that there is enoughmargin to prevent punch-through in CMOS circuits. For example, thetrench 28 separates the source/drain regions 22 of one pixel from theactive layer of an adjacent pixel. Accordingly shallow trenches aregenerally sufficiently wide to allow a margin adequate enough to preventpunch-through or current leakage. The invention further provides noveltechniques for preventing current leakage while allowing tighter designrules in CMOS circuits.

[0041] A first embodiment according to the invention is now describedwith reference to FIGS. 2-6. Applicant proposes an STI process, whichuses an isolation trench filled with a doped conductive materialcontaining silicon. Shallow trench isolation regions for CMOS imagesensors generally have a depth of less than about 3000 Angstroms andgenerally around about 2000 to about 2500 Angstroms. Typically, shallowtrench regions are filled with a conventional insulator, such as oxidesor high density plasma (HDP) oxides. However, it is difficult to filltrenches having a depth greater than 2500 Angstroms with conventionalinsulators due to the limited spacing within the trench, for example,undesirable voids or air gaps are formed when oxides are used to filltrenches having a depth greater than about 2500 Angstroms. In accordancewith the first embodiment of the invention, Applicants propose fillingtrenches with conductive materials containing silicon, preferablypolysilicon or silicon-germanium. Conductive materials containingsilicon may be easily deposited into trenches of various depths, unlikeconventional insulation materials, e.g., silicon dioxide, siliconnitride, NO, ON, HDP, and ONO, which are difficult to fill in deeptrenches. Thus, using a conductive material containing silicon to fillthe trench 328 will allow easy formation of a trench, particularly, adeep trench having a depth greater than about 2000 Angstroms, andpreferably about 4000 to about 5000 Angstroms.

[0042] Generally, the deeper the trench the better the isolation. Withrespect to CMOS image sensors in particular, the deeper the trench thehigher the electron storage capacitance of the CMOS image sensor. Atrench according to the invention is deeper than a shallow trench, andaccordingly has longer sidewalls than a shallow trench. Therefore, thelonger sidewalls allow for a larger electrical connection region 323along the sidewalls of the trench such that electron storagecapacitance, e.g., hole accumulation, in the electrical connectionregion 323 is increased in accordance with the invention.

[0043] In a CMOS image sensor having a trench filled with a conductivematerial containing silicon in accordance with the present invention, asshown in FIG. 2, a trench 328 is etched into a doped active layer 320. Aresist and mask are applied, and photolithographic techniques are usedto define the area to be etched-out. A directional etching process, suchas Reactive Ion Etching (RIE), or etching with a preferentialanisotropic etchant is used to etch into the doped active layer 320 toform the trench 328. The resist and mask are removed leaving a structurethat appears as shown in FIG. 2.

[0044] Referring now to FIG. 3, an oxide, i.e., SiO₂ or other dielectricliner 327 is grown within the trench 328. The oxide liner may be formedof NO, ON, or ONO among many other suitable materials. The dielectricliner 327 may be substantially conformal. In other words, the thicknessof the liner 327 is substantially the same along the sidewalls 319 andat the bottom of the trench 328. In general, the thickness of thedielectric liner 327 along the sidewalls should be at least about 100Angstroms.

[0045] Referring now to FIG. 4, a highly doped (in-situ doped) n-type orp-type conductive material containing silicon 329 is deposited to fillthe trench 328. Suitable conductive materials containing silicon includepolysilicon and silicon-germanium. Alternatively, as shown in FIG. 5,the trench 328 may be filled with a conductive material containingsilicon 329 then, a masked ion implant (indicated by arrows) may beperformed to dope the conductive material containing silicon. Forexample, in the case of a p-type active layer 320, with p-type wells,p-type ions such as boron (B) can be implanted into the conductivematerial containing silicon using a photoresist mask 326. Similarly, inthe case of an n-type active layer 320 with n-type wells, n-type ionssuch as phosphorous (P), arsenic (As), or antimony (Sb) can beimplanted.

[0046] Conductive materials containing silicon are easily filled intodeep trenches. The deeper the trench, the harder it is to fill thetrench with conventional insulators. Oxides and other conventionalinsulators form voids or air gaps when used to fill deep trenches.However, in accordance with the invention, a trench may be filled with aconductive material containing silicon easily and effectively.

[0047] An exemplary CMOS image sensor in accordance with the inventionand having a pinned photodiode 321 is shown in FIG. 6. The pinnedphotodiode 321 has a p-type surface layer 324 and an n-type photodioderegion 326 within a p-type active layer 320. A junction is formed aroundthe entirety of the n-type region 326. An impurity doped floatingdiffusion region 325, preferably having n-type conductivity, is providedon one side of the channel region of transfer gate 350, the other sideof which has a portion of n-type region 326. A trench isolation region328 is formed in the active layer 320 adjacent to but spaced from then-type region 321. An electrical connection region 323 for providinghole accumulation is formed adjacent the sidewalls of the trenchisolation region 328. The trench isolation region 328 is formed asdescribed above with respect to FIGS. 2-5.

[0048] The gate stacks, for example the transfer gate 350, may be formedbefore or after the trench is etched. The order of these process stepsmay be varied as is required or convenient for a particular processflow, for example, if a photogate sensor which overlaps the transfergate is desired, the gate stacks must be formed before the photogate,but if a non-overlapping photogate is desired, the gate stacks may beformed after photogate formation.

[0049] A translucent or transparent insulating layer 330 is formed overthe CMOS image sensor 300. Conventional processing methods are thencarried out to form for example, contacts (not shown) in the insulatinglayer 330 to provide an electrical connection to the source/drainregions 322, the floating diffusion region 325, and other wiring toconnect gate lines and other connections in the sensor 300. For example,the entire surface may then be covered with a passivation layer, ofe.g., silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized andetched to provide contact holes, which are then metallized to providecontacts to the photogate (if used), reset gate, and transfer gate.

[0050] The use of a trench in accordance with the invention providesimproved isolation between pixels. The deeper trench better inhibitselectrons from diffusing under the isolation trench to an adjacent pixelthereby preventing cross-talk between neighboring pixels. Accordingly,by enhancing isolation via a deeper trench, additional implants underthe trench are not necessary, therefore by reducing the implants neededfor isolation, current leakage is also reduced. Another advantage of theinvention, is that the use of a deep trench filled with a conductivematerial containing silicon in accordance with the invention provides adeeper hole accumulation region, thereby increasing electron storagecapacity. Also the deeper trench allows for tighter isolation designrules. Deeper trenches may also be narrower than shallow trenches, whilestill providing effective isolation between neighboring regions.Accordingly, the source/drain regions of one pixel may be brought closerto the active layer of an adjacent pixel, by narrowing the width of thedeep trench.

[0051] A second embodiment in accordance with the invention is nowdescribed with reference to FIGS. 7-13. Referring now to FIG. 7, atrench 428 is etched into an active layer 420. The trench is preferablya deep trench having a depth greater than about 2500 Angstroms andpreferably between about 4000 to about 5000 Angstroms. A resist and maskare applied, and photolithographic techniques are used to define thearea to be etched-out. A directional etching process, such as RIE, oretching with a preferential anisotropic etchant is used to etch into thedoped active layer 420 to form the trench 428. The resist and mask areremoved leaving the FIG. 7 structure.

[0052] Referring now to FIG. 8, a nitride liner 432 is formed in thetrench 428 via Chemical Vapor Deposition (CVD). This nitride liner 432may be formed of any suitable nitride including NO, ON, ONO, and ispreferably formed of silicon nitride.

[0053] Referring now to FIG. 9, an oxide, e.g. SiO₂ or other dielectricliner 427 is formed within the trench 428 and over the silicon nitrideliner 432. The liner 427 may be non-conformal, in that its thickness mayvary along the trench sidewalls 429. A relatively thick liner can beformed near the bottom of the trench and a thinner liner formed near thetop of the trench. Non-conforming materials such as the well-known PSG,BPSG, SOG can be used to produce the liner 427.

[0054] Referring now to FIG. 10, a bottom portion of the oxide liner 427and nitride liner 432 is stripped away. This can be accomplished by ananisotropic dry etch or a masked wet or dry etch.

[0055] Referring now to FIG. 11, a selective epitaxial layer 433 isgrown to fill the trench 428 with silicon. The epitaxial layer 433 maybe grown using any suitable technique and may be grown as a single layeror multi-layer. The epitaxial layer 443 is grown in directly on asurface of the active layer 420 so as to provides a direct electricalcontact to the doped active layer 420 through the trench while providingimproved field isolation between pixels. Providing a direct electricalcontact to the active layer in accordance with the invention, eliminatesthe need for a top contact, therefore saving space and allowing fortighter pixel formation.

[0056] Referring now to FIG. 12, in accordance with yet anotherembodiment of the invention, the selective epitaxial layer 433 is grownto partially fill the trench 428 with silicon.

[0057] Referring now to FIG. 13, a deposition process is performed tofill the rest of the trench with a filler material 434. The fillermaterial is preferably an oxide material and is more preferably an HDPoxide. Alternatively, a conductive material containing silicon, forexample polysilicon or silicon-germanium, may also be used to fill therest of the trench 428.

[0058] By providing an epitaxial layer 433, the amount of oxide neededto fill the trench is reduced. Accordingly by using a reduced amount ofoxide, or not using oxide in situations where conductive materialcontaining silicon is used to fill the rest of the trench or when thetrench is filled with the epitaxial layer 433 (as shown in FIG. 11), adeep trench in accordance with the invention may be formed. As discussedabove deep trenches provide improved isolation and in the case of CMOSimage sensors, prevention of cross-talk between adjacent pixels. Andalso as discussed above with regard to the first embodiment, the use ofa deep trench to provide improved isolation eliminates the need to useexcess implants beneath the trench, thereby reducing dark current inCMOS image sensors caused by current leakage. A selective-EPI filled orpartially filled trench according to the invention may be used incombination with other aspects of the invention, for example, theselective-EPI-partially filled trench may be used along with a deeptrench filled with a conductive material containing silicon.

[0059] An exemplary CMOS image sensor in accordance with the inventionand having a pinned photodiode 421 is shown in FIG. 14. The pinnedphotodiode 421 has a p-type surface layer 424 and an n-type photodioderegion 426 within a p-type active layer 420. A junction is formed aroundthe entirety of the n-type region 426. An impurity doped floatingdiffusion region 425, preferably having n-type conductivity, is providedon one side of the channel region of transfer gate 450, the other sideof which has a portion of n-type region 426. A trench isolation region428 is formed in the active layer 420 adjacent to but spaced from n-typeregion 421. An electrical connection region 423 for providing holeaccumulation is formed adjacent the sidewalls of the trench isolationregion 428. The trench isolation region 428 is formed as described abovewith respect to FIGS. 7-13.

[0060] The gate stacks, for example transfer gate 450, may be formedbefore or after the trench is etched. The order of these preliminaryprocess steps may be varied as is required or convenient for aparticular process flow, for example, if a photogate sensor whichoverlaps the transfer gate is desired, the gate stacks must be formedbefore the photogate, but if a non-overlapping photogate is desired, thegate stacks may be formed after photogate formation.

[0061] A translucent or transparent insulating layer 430 is formed overthe CMOS image sensor 400. Conventional processing methods are thencarried out to form for example, contacts (not shown) in the insulatinglayer 430 to provide an electrical connection to the source/drainregions, the floating diffusion region 425, and other wiring to connectgate lines and other connections in the sensor 400. For example, theentire surface may then be covered with a passivation layer, of e.g.,silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etchedto provide contact holes, which are then metallized to provide contactsto the photogate (if used), reset gate, and transfer gate.

[0062] Pixel arrays according to the invention, and described withreference to FIGS. 2-14, may be further processed as known in the art toarrive at CMOS image sensors having the functions and features of thosediscussed with reference to FIGS. 2-14.

[0063] A typical processor based system, which includes a CMOS imagesensor according to the invention is illustrated generally at 642 inFIG. 15. A processor based system is exemplary of a system havingdigital circuits, which could include CMOS image sensors. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision, vehicle navigation, video phone, surveillancesystem, auto focus system, star tracker system, motion detection system,image stabilization system and data compression system forhigh-definition television, all of which can utilize the presentinvention.

[0064] A processor based system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 644, for example, amicroprocessor, that communicates with an input/output (I/O) device 646over a bus 652. The CMOS image sensor 642 also communicates with thesystem over bus 652. The computer system 600 also includes random accessmemory (RAM) 648, and, in the case of a computer system may includeperipheral devices such as a flash memory card 654, or a compact disk(CD) ROM drive 656 which also communicate with CPU 644 over the bus 652.It may also be desirable to integrate the processor 654, CMOS imagesensor 642 and memory 648 on a single IC chip.

[0065] The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as being limited by the foregoing description anddrawings, but is only limited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A structure for isolating areas in asemiconductor device, said structure comprising: a trench formed in animage sensor substrate between adjacent regions; and a conductivematerial deposited within said trench to fill at least a portion of saidtrench.
 2. The structure of claim 1 further comprising an insulatingliner formed along at least sidewalls of said trench.
 3. The structureof claim 1 wherein said conductive material has an n-type conductivity.4. The structure of claim 1 wherein said conductive material has ap-type conductivity.
 5. The structure of claim 1 wherein said conductivematerial comprises silicon.
 6. The structure of claim 5 wherein saidconductive material comprises silicon-germanium.
 7. The structure ofclaim 1 wherein said trench further comprises an epitaxial layerunderlying said conductive material and formed within said trench. 8.The structure of claim 1 wherein said trench has a depth of betweenabout 1000 to about 5000 Angstroms.
 9. The structure of claim 1 whereinsaid trench has a depth of greater than about 2000 Angstroms.
 10. Thestructure of claim 5 wherein said conductive material comprisespolysilicon.
 11. The structure of claim 1 wherein said semiconductordevice comprises a CMOS image sensor.
 12. The structure of claim 1wherein said conductive material comprises an epitaxial material.
 13. Astructure for isolating areas in an image sensor, said structurecomprising: a trench formed in an image sensor substrate betweenadjacent pixels; an insulating liner formed along walls of said trench;and a conductive material formed within said insulating liner.
 14. Thestructure of claim 13 wherein said conductive material comprises anepitaxial layer.
 15. The structure of claim 14 wherein said epitaxiallayer partially fills said trench.
 16. The structure of claim 15 furthercomprising a filler material deposited over said epitaxial layer andwithin said trench.
 17. The structure of claim 13 wherein saidinsulating liner comprises an oxide material.
 18. The structure of claim17 wherein said insulating liner comprises NO.
 19. The structure ofclaim 17 wherein said insulating liner comprises ON.
 20. The structureof claim 17 wherein said insulating liner comprises ONO.
 21. Thestructure of claim 13 wherein said insulating liner is non-conformal.22. The structure of claim 13 further comprising a nitride liner formedbetween said sidewalls of said trench and said insulating liner.
 23. Thestructure of claim 22 wherein said nitride liner comprises siliconnitride.
 24. The structure of claim 22 wherein said nitride linercomprises NO.
 25. The structure of claim 22 wherein said nitride linercomprises ON.
 26. The structure of claim 22 wherein said nitride linercomprises ONO.
 27. The structure of claim 16 wherein said fillermaterial comprises an insulating material.
 28. The structure of claim 16wherein said filler material comprises a conductive material.
 29. Thestructure of claim 28 wherein said filler material comprises silicon.30. The structure of claim 29 wherein said filler material comprisespolysilicon.
 31. The structure of claim 29 wherein said filler materialcomprises silicon-germanium.
 32. The structure of claim 27 wherein saidinsulating material comprises an oxide.
 33. The structure of claim 32wherein said insulating material comprises an HDP oxide.
 34. Thestructure of claim 14 wherein said epitaxial layer provides a directelectrical contact to a doped active layer of said image sensorsubstrate.
 35. An image sensor comprising: an active layer of a firstconductivity type formed in a substrate; a charge transfer region formedin said active layer; a photodiode formed in said active layer adjacentsaid charge transfer region, said photodiode comprising a region of asecond conductivity type between regions of said active layer of saidfirst conductivity type; a charge collection region in said active layerfor receiving charges transferred from said photodiode region; anisolation region formed adjacent said active layer, said isolationregion comprising a trench; and a conductive material formed within saidtrench.
 36. The sensor of claim 35 further comprising an insulatingliner formed along at least sidewalls of said trench.
 37. The sensor ofclaim 35 wherein said conductive material comprises silicon.
 38. Thesensor of claim 37 wherein said conductive material comprisespolysilicon.
 39. The sensor of claim 37 wherein said conductive materialcomprises silicon-germanium.
 40. The sensor of claim 35 wherein saidtrench has a depth of between about 1000 to about 5000 Angstroms. 41.The sensor of claim 35 wherein said trench has a depth of greater thanabout 2000 Angstroms.
 42. The sensor of claim 35 wherein said conductivematerial comprises an epitaxial material.
 43. The sensor of claim 42wherein said epitaxial material partially fills said trench.
 44. Thesensor of claim 43 further comprising a filler material deposited oversaid epitaxial material and within said trench.
 45. The sensor of claim36 wherein said insulating liner comprises an oxide material.
 46. Thesensor of claim 36 wherein said insulating liner is non-conformal. 47.The sensor of claim 36 further comprising a nitride liner formed betweensaid sidewalls of said trench and said insulating liner.
 48. The sensorof claim 44 wherein said filler material comprises an insulatingmaterial.
 49. The sensor of claim 44 wherein said filler materialcomprises a conductive material containing silicon.
 50. The sensor ofclaim 49 wherein said conductive material containing silicon comprisespolysilicon.
 51. The sensor of claim 49 wherein said conductive materialcontaining silicon comprises silicon-germanium.
 52. The sensor of claim42 wherein said epitaxial material provides a direct electrical contactto said active layer of said image sensor substrate.
 53. A processingsystem comprising: (i) a processor; and (ii) a semiconductor devicecoupled to said processor and including: a trench formed in a substratebetween adjacent regions; and a conductive material deposited withinsaid trench to fill at least a portion of said trench.
 54. The system ofclaim 53 further comprising an insulating liner formed along at leastsidewalls of said trench.
 55. The system of claim 53 wherein saidconductive material has an n-type conductivity.
 56. The system of claim53 wherein said conductive material has a p-type conductivity.
 57. Thesystem of claim 53 wherein said conductive material comprises silicon.58. The system of claim 57 wherein said conductive material comprisespolysilicon.
 59. The system of claim 57 wherein said conductive materialcomprises silicon-germanium.
 60. The system of claim 53 wherein saidconductive material comprises an epitaxial layer.
 61. The system ofclaim 53 wherein said trench further comprises an epitaxial layerunderlying said conductive material.
 62. The system of claim 53 whereinsaid trench has a depth of between about 1000 to about 5000 Angstroms.63. The system of claim 53 wherein said trench has a depth of greaterthan about 2000 Angstroms.
 64. The system of claim 54 wherein saidinsulating liner comprises an oxide material.
 65. The system of claim 54wherein said insulating liner is non-conformal.
 66. The system of claim54 further comprising a nitride liner formed between said sidewalls ofsaid trench and said insulating liner.
 67. The system of claim 60further comprising a filler material deposited over said epitaxial layerand within said trench.
 68. The system of claim 67 wherein said fillermaterial comprises an insulating material.
 69. The system of claim 68wherein said insulating material comprises an oxide.
 70. The system ofclaim 69 wherein said insulating material comprises an HDP oxide. 71.The system of claim 60 wherein said epitaxial layer provides a directelectrical contact to an active layer of said substrate.
 72. Aprocessing system comprising: (i) a processor; and (ii) an image sensordevice coupled to said processor, said image sensor device comprising:an active layer of a first conductivity type formed in a substrate; acharge transfer region formed over said substrate; a photodiode formedadjacent said charge transfer region, said photodiode comprising aregion of a second conductivity type sandwiched between regions of saidactive layer of said first conductivity type; a charge collection regionfor receiving charges transferred from said photodiode region; anisolation region formed adjacent interconnecting first conductivity typeportions of said active layer, said isolation region comprising atrench; and a conductive material formed at least partially within saidtrench.
 73. The system of claim 72 further comprising an insulatingliner formed along at least sidewalls of said trench.
 74. The system ofclaim 72 wherein said conductive material comprises silicon.
 75. Thesystem of claim 72 wherein said conductive material comprises anepitaxial layer.
 76. The system of claim 75 further comprising a fillermaterial formed over said conductive material and within said trench.77. The system of claim 76 wherein said filler material comprises aninsulating material.
 78. The system of claim 72 wherein said trench hasa depth of between about 1000 to about 5000 Angstroms.
 79. The system ofclaim 72 wherein said trench has a depth of greater than about 2000Angstroms.
 80. A method of forming a structure for isolating areas in asemiconductor device, said method comprising: forming a trench toseparate regions of a semiconductor device; and at least partiallyfilling said trench with a conductive material.
 81. The method of claim80 further comprising forming an insulating liner along at leastsidewalls of said trench.
 82. The method of claim 80 further comprisingdoping said conductive material with an n-type conductivity.
 83. Themethod of claim 80 further comprising doping said conductive materialwith a p-type conductivity.
 84. The method of claim 80 wherein saidconductive material comprises silicon.
 85. The method of claim 84wherein said conductive material comprises polysilicon.
 86. The methodof claim 84 wherein said conductive material comprisessilicon-germanium.
 87. The method of claim 80 further comprising formingan epitaxial layer underlying said conductive material.
 88. The methodof claim 80 wherein said trench is formed to have a depth of betweenabout 1000 to about 5000 Angstroms.
 89. The method of claim 80 whereinsaid trench is formed to have a depth of greater than about 2000Angstroms.
 90. A method of forming a structure for isolating areas in asemiconductor device, said method comprising the steps of: forming anopening in an active area of a semiconductor substrate between adjacentregions; growing an epitaxial layer in said opening; and depositing afiller material within said opening and over said epitaxial layer tofill said opening.
 91. The method of claim 90 wherein forming saidopening comprises forming a trench having a depth of greater than about2000 Angstroms.
 92. The method of claim 90 further comprising forming afirst liner in said opening before growing said epitaxial layer andbefore depositing said filler material and removing a bottom portion ofsaid first liner before growing said epitaxial layer.
 93. The method ofclaim 92 wherein said first liner comprises an oxide.
 94. The method ofclaim 90 wherein said filler material comprises a conductive materialcontaining silicon.
 95. The method of claim 90 wherein said fillermaterial comprises an insulating material.
 96. The method of claim 95wherein said insulating material comprises an oxide.
 97. The method ofclaim 92 comprising forming said first liner non-conformally.
 98. Themethod of claim 92 further comprising forming a second liner betweenwalls of said opening and said first liner and removing a bottom portionof said second liner before growing said epitaxial layer.
 99. The methodof claim 98 wherein said second liner comprises nitride.
 100. The methodof claim 90 comprising forming a direct electrical contact to a dopedactive layer of a substrate through said epitaxial layer.
 101. A methodof forming an image sensor, said method comprising the steps of: forminga substrate; forming an active layer of a first conductivity type withinsaid substrate; forming a charge transfer region within said activelayer; forming a photodiode within said active layer adjacent saidcharge transfer region, said step of forming said photodiode comprisingforming a region of a second conductivity type between regions of saidactive layer of said first conductivity type; forming a chargecollection region within said active layer for receiving chargestransferred from said photodiode region; and forming an isolation regionadjacent said active layer, by forming a trench at least partiallyfilling said trench with a conductive material.
 102. The method of claim101 wherein said step of forming said trench further comprises formingan insulating liner along at least sidewalls of said trench.
 103. Themethod of claim 101 further comprising doping said conductive materialwith an n-type conductivity implant.
 104. The method of claim 101further comprising doping said conductive material with a p-typeconductivity implant.
 105. The method of claim 101 wherein saidconductive material comprises silicon.
 106. The method of claim 105wherein said conductive material comprises polysilicon.
 107. The methodof claim 105 wherein said conductive material comprisessilicon-germanium.
 108. The method of claim 101 wherein said step offorming said trench further comprises forming an epitaxial layerunderlying said conductive material.
 109. The method of claim 101wherein said trench is formed to have a depth of between about 1000 toabout 5000 Angstroms.
 110. The method of claim 101 wherein said trenchis formed to have a depth of greater than about 2000 Angstroms.